The present invention relates to a semiconductor device, and in particular, to a semiconductor device operating as a switching circuit having at least one field-effect transistor (FET).
Description of the Related Art
There is a conventional semiconductor device that functions as a semiconductor switching circuit employing four FETs including source and drains thereof configured to oppose each other at positions of symmetry in a comb shape and gates disposed therebetween (reference is to be made to the Japanese Patent Laid-Open Publication No. 63-67802 entitled "Switching Circuit").
In FIG. 1A thereof is a plan view showing an example of the semiconductor device of the prior art and FIG. 1B is a circuit diagram of the circuit construction of FIG. 1A. In the device of the conventional technology, there are included four FETs 37 to 40. As can be seen from FIG. 1A, each FET includes a source region 32 and a drain region 33 arranged respectively at opposing positions of symmetry in a comb contour and a gate region 31 manufactured between the source region 32 and the drain region 33. In the FETs 37 and 38, the source regions 32 thereof are connected to each other to be commonly linked with an input terminal 34. The drain regions 33 of the FETs 39 and 40 are respectively coupled with the drains 33 of the FETs 37 and 38 to be commonly connected to output terminals 35 and 36, respectively.
Consequently, the semiconductor device has an equivalent circuit as shown in FIG. 1B in which the source 32 of the FETs 37 and 38 is connected to the input terminal 34, the drain 33 of the FETs 37 and 38 is connected the drain 33 and the output terminals 35 and 36. In this structure, the source 32 of the FETs 39 and 40 is grounded.
In the semiconductor device, the gates 31 of the FETs 37 and 40 receive a first switching signal and the gates 31 of the FETs 38 and 39 receive a second switching signal, the first switching signal being obtained by logically inverting the second switching signal. Therefore, a microwave signal supplied to the input terminal 34 is selected as an output signal from either one of the output terminals 35 and 36. In short, according to the logical values respectively of the first and second switching signals, the input signal can be obtained from either one of the output terminals 35 and 36.
In this regard, for each of the FETs of the switch, the drain-source resistance Rds in the on state of the FET should be decreased; whereas, when the FET is off, the drain-source capacitance Cds should be lowered. Ordinarily, the drain-source resistance Rds increases in inverse proportion to the gate width of the FET and the drain-source capacitance Cds soars in proportion to the gate width.
Consequently, an optimal combination of Rds and Cds can be obtained by optimizing the gate width. For this purpose, in the conventional semiconductor device shown in FIG. 12, to prevent the increase in the capacitance Cds due to intersections between the gate and source electrodes and/or between the gate and drain electrodes, the source 32 and drain 33 are arranged to oppose to each other at positions of symmetry in the comb shape. To increase the gate width, the gate 31 is fabricated in a folded contour between the source 32 and drain 33 in the plan view.
However, it has been known in a case in which a chemical semiconductor substrate highly sensitive to the ion bond that the characteristic of the FET, for example, the drain-source resistance Rds is increased depending on the direction of the gate. In the resulting conventional semiconductor device including the gate region 31 folded to decrease the drain-source resistance Rds as shown in FIG. 1A, there may occur a disadvantage of increase in the resistance Rds depending on cases. In short, the folded structure of the gate region 31 is not suitable for the FET used in the switching circuit.
Additionally, the capacitance resulting from intersections between the gate and source electrodes and/or between the gate and drain electrodes becomes almost negligible when the air bridge technology is employed. In consequence, the semiconductor device of the prior technology is attended with a problem regarding the minimization in size and improvement of the performance in addition to a relatively large area occupied by the folded shape of the gate region 31.
Incidentally, the switching circuits include many types of circuits such as a circuit of single pole single throw (SPST) type and a circuit of single pole double throw (SPDT) type. As can be seen from FIG. 1B, the conventional semiconductor device includes an SPDT circuit. However, applications thereof to other circuit types and other configurations employing a plurality of FETs have not been described in the article.